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AS7C33128NTD32A - 3.3V 128K X 32/36 SRAM

Description

The AS7C33128NTD36A family is a high performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) device organized as 131,072 words × 32 or 36 bits that incorporates a LATE LATE Write.

Features

  • Organization: 131,072 words × 32 or 36 bits NTD™1 architecture for efficient bus operation.
  • Fast clock speeds to 166 MHz in LVTTL/LVCMOS.
  • Fast clock to data access: 3.5/4.0/5.0 ns.
  • Fast OE access time: 3.5/4.0/5.0 ns.
  • Fully synchronous operation.
  • Flow-through or pipelined mode.
  • Asynchronous output enable control 1. NTD™ is a trademark of Alliance Semiconductor Corporation. Logic block diagram.
  • Economical 100-pin TQFP packa.

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Datasheet preview – AS7C33128NTD32A

Datasheet Details

Part number AS7C33128NTD32A
Manufacturer Alliance Semiconductor
File Size 161.42 KB
Description 3.3V 128K X 32/36 SRAM
Datasheet download datasheet AS7C33128NTD32A Datasheet
Additional preview pages of the AS7C33128NTD32A datasheet.

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Full PDF Text Transcription

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December 2002 AS7C33128NTD32A AS7C33128NTD36A Š 9 .î 65$0 ZLWK 17'TM Features • Organization: 131,072 words × 32 or 36 bits NTD™1 architecture for efficient bus operation • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/4.0/5.0 ns • Fast OE access time: 3.5/4.0/5.0 ns • Fully synchronous operation • Flow-through or pipelined mode • Asynchronous output enable control 1. NTD™ is a trademark of Alliance Semiconductor Corporation. Logic block diagram • Economical 100-pin TQFP package • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.
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